The Georgia Tech TechFee program provides an opportunity for GT faculty and staff to submit proposals on behalf of instructors and students for resources that are dedicated to classroom educational and research experiences. These TechFee proposals are funded via student technology fees, so their primary purpose is to provide novel equipment that helps to further student instructional and unfunded (ie, undergraduate) research aims. CRNCH is proud to help utilize our expertise in supporting novel accelerators to provide access to TechFee-funded equipment for class and student usage.
Note: If you are an instructor looking to use these resources for a course, please email the PI, Jeffrey Young with information on your class use case. If you are a GT student, you can request an account on the Rogues Gallery using the online form.
Funded TechFee Proposals Hosted by Rogues Gallery
FY 2020 - Reconfigurable Cluster Initiative
Funded amount: $74,905
PIs: Jeffrey Young, Hyesoon Kim, Jason Riedy, Lee Lerner
Proposed Overview: This initiative proposes to acquire up to nine Field Programmable Reconfigurable Array (FPGA) devices and two host servers to seed a new reconfigurable cluster initiative. This cluster will initially be used by Atlanta-based students in multiple courses but will eventually be extended to support a limited number of OMSCS students via remote access and cluster-based scheduling. We anticipate supporting undergraduate students and graduate students for coursework as well as making the resource available to all interested students via our existing TSO-supported testbed, the “Rogues Gallery”. This effort will provide easier access to novel hardware for students as well as reduce the need for individual professors to acquire and maintain this type of hardware for their classes.
Status Update: Due to the COVID-19 pandemic, remote access to novel FPGA hardware has become more critical than ever. CRNCH has pushed ahead with supporting devices that can be remotely accessed and power cycled. All of our deployed equipment can be accessed from off campus by enrolled students, and we are working on Slurm scheduling to support larger class usage.
Thanks to: Tool support is provided by Intel donations and the Xilinx University Program (XUP). Many thanks also to the XUP program for the donation of U280 cards for research and teaching support.
What’s available for class and student use?:
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FPGA Board / DevKit
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FPGA
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Memory
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Programming Tools
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Notes
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Hosting Machine | |
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GX1150
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8 GB DDR4
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Intel SDK, OneAPI
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Flubber | ||
| Intel Stratix 10 PAC | Coming soon | 16 GB DDR3 | Coming soon | Flubber | ||
| Bittware 520N-MX | GX2800 | 16 GB DDR4 | Intel SDK, OpenCL | Flubber | ||
| Mellanox Innova-2 Flex SmartNIC | Kintex Ultrascale XCKU15P | 8 GB DDR4 | Xilinx Vivado | Connect-X 5 SmartNICs with FPGA chips | Flubber | |
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Zynq XC7Z020-1CLG400C
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512MB DDR3
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Xilinx Vivado, PYNQ
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Also available for Nengo-FPGA
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Brainard | ||
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Zynq UltraScale+ MPSoC XCZU7EV-1FBVB900E
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DDR4
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Xilinx Vitis, Vivado
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Brainard | ||
| Zynq UltraScale+ MPSoC Evaluation Kit | Zynq Ultrascale+ MPSoC XCZU7EV-2FFVC1156 | DDR4, 4 GB | Xilinx Vitis, Vivado, PYNQ | Brainard | ||
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Ultrascale+ XCU280
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8 GB HBM2
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Xilinx Vitis, Vivado, Vitis AI
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Supported in part by XUP
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Flubber, multiple cards | ||
| Raspberry Pi 4 | Used to host FPGA Devkits | 4 GB DDR2 | OpenMP | Used to support PYNQ and devkit usage | Brainard | |
| Coral TPU | Quad Cortex-A53, Cortex-M4F, Google Edge TPU | 1 GB LPDDR4 | TensorFlow Lite | Devkit that allows for alternate AI comparisons with TPU units. | Brainard | |
| Intel Movidius Neural Stick 2 | OpenVino | Devkit that allows for alternate AI comparisons | Brainard | |||
| Jetson Xavier NX | 6-core Arm Carmel CPU, 384 V100 cores | 8 GB DDR4 | OpenMP, CUDA | Devkit that allows for alternate AI comparisons | Brainard |
What classes have made use of this resource?
Please note that this list may change as resources must typically be deployed one semester before class usage.
- ECE 2601, 3601, 4601 (VIP)
- CS 3220
- CS 2698/4698 (Undergraduate Research)
- As of Fall 2020, ~35 students have access to the CRNCH reconfigurable resources for academic-related projects.
Additionally we are seeking opportunities to utilize this hardware for machine learning-related classes like CS 4803 / 7643 and digital design classes like ECE 2031. Special topics projects like CS8803 (Topics on Datacenter Design, Dr. Alex Daglis) also are planned to make use of Xilinx-based smartNICs for optional class projects.
Tools Available: Intel FPGA SDK 2019 (19.3, 20.1), Intel Devstack, Xilinx Vitis and Vivado 19.2, 20.1, Xilinx PYNQ
Primary Contact: Jeffrey Young
Restrictions: Techfee equipment is prioritized for instructional usage. General student usage can occur on an ad-hoc basis but is scheduled at a lower priority.
