Jan 28, 2019 | Atlanta, GA
Georgia Tech researchers have been awarded $4.5 million to build new programming systems for developing data-intensive algorithms with automatic software and hardware co-optimization. The project is named Dynamic Data-Aware Reconfiguration, INtegration and Generation (DDARING).
School of Computer Science Professors and Co-Directors of the Center for Research into Novel Computing Hierarchies (CRNCH) Vivek Sarkar and Tom Conte and School of Computational Science and Engineering’s Chair David Bader and Associate Professor Richard Vuduc are co-investigators on this project from Tech. The award will also be used to support research collaborators at University of Illinois, University of Michigan, and University of Southern California.
“This is a unique opportunity to address post-Moore computing challenges through new research on software and hardware co-optimization by adapting the hardware to executing applications and the data sets being analyzed,” said Sarkar. “Advancing data analysis algorithms and pushing the boundaries of hardware are areas of strength for Georgia Tech, and we’re excited to work with our partners at Illinois, Michigan, and USC on this important challenge for future computing platforms.”
The project is part of the Defense Advanced Research Project Agency’s (DARPA) Electronics Resurgence Initiative (ERI), a five-year upwards of $1.5 billion investment in the future of domestic electronic systems. Building on the tradition of other successful government-industry partnerships, ERI aims to forge forward-looking collaborations among the commercial electronics community, defense industrial base, university researchers, and the Department of Defense. They expect to create a more specialized, secure, and heavily automated electronics industry that serves the needs of both the domestic commercial and defense sectors. Tech researchers will work under the Software Defined Hardware (SDH) program, which creates malleable hardware/software architectures that allow an application to defer hardware configuration to runtime.
This research seeks to enable developers to easily create applications while the new system automatically optimizes their performance on new and emerging architectures. These improvements will make architectures more energy efficient for data analytics applications, including those in the machine learning and artificial intelligence domains.
“Under this program, our project should make programming next-generation hardware easy and productive,” said Bader. “We are looking at novel software and hardware co-design that lets users rapidly take advantage of new architectural features.”
The program goals also fit with CRNCH’s mission to find new paths forward in this post-Moore’s law age, when the number of transistors on a chip cannot be expected to double every 1.5 to 2 years, as it has for decades.